FIG. 1 shows an integrated semiconductor memory 100, for example, a DRAM (dynamic random access memory) semiconductor memory, which includes a memory cell array 10, a control circuit 20 with a control terminal S20, and an address register 30 with an address terminal A30. The memory cell array 10 is subdivided into different memory banks 10a, 10b, 10c, 10d. Each memory bank has a plurality of memory blocks SB. Within the memory blocks, memory cells are arranged along word and bit lines. A data terminal DQ serves for reading data into and out of the memory cells.
For controlling the mode of operation of the integrated semiconductor memory, the integrated semiconductor memory includes a control circuit 20 with a control terminal S20. Depending on the control signal applied externally to the control terminal S20, write and read operations are monitored and controlled by the control circuit 20. For this purpose, the control circuit 20 generates internal control signals S1, S2, S3 to drive further components of the integrated semiconductor memory, for example, the memory cell array or voltage generators.
FIG. 2 shows, in enlarged fashion, the memory block SB within the memory bank 10d as illustrated in FIG. 1. The memory block SB includes a plurality of segmented word line drivers arranged in strips SW within the memory block SB. On both sides of each segmented word line driver strip SW, the memory cells SZ are arranged at crossover points of word lines WL and bit lines BL. For accessing one of the memory cells SZ arranged along the word line with the word line address X=0, the word line WL is activated by the associated segmented word line driver.
For faster activation of a word line, recent memory generations do not have a central word line driver, but rather additional intermediate amplifiers that drive a large word line capacitance of the word line connected to them. The use of the intermediate amplifiers within the segmented word line driver strip SW results in a faster propagation time for a word line signal and thus a faster access time overall.
FIG. 3 shows an enlarged illustration of the segmented word line driver strip SW from FIG. 2 with a first intermediate amplifier comprising the switching transistors 11, 12, 13, and a second intermediate amplifier comprising the switching transistors 11′, 12′, 13′. The first intermediate amplifier activates the word line WL, whereas the second intermediate amplifier activates the word line WL′. Memory cells SZ1, SZ2 are connected to the word lines WL, WL′.
In the case of a DRAM semiconductor memory, a memory cell SZ, as illustrated, for example, for the memory cell SZ1, includes a selection transistor AT and a storage capacitor SC. The selection transistor AT is controlled into the on state by a control signal on the word line WL and, in this state, connects the storage capacitor to the connected bit line for reading an item of information into and out of the memory cell. By a corresponding word line signal on the word lines WL and WL′, the memory cell SZ1 and the memory cell SZ2 are conductively connected to the bit line BL1 and the bit line BL2, respectively.
The two intermediate amplifiers of FIG. 3 are identical in terms of their construction, for which reason the construction is described here only with reference to the first intermediate amplifier. Via the n-channel transistor 11, the word line WL is connected to a terminal D1 for applying a voltage potential VWL. Via the p-channel transistor 12, the word line is connected to a terminal D2 for applying a voltage potential VPP and for applying a ground potential GND. Via the n-channel transistor S13, which is controlled by control voltage potentials VWL and Vint at its control terminal S13, the word line WL is connected to the terminal D1 for applying the voltage potential VWL. The switching transistors 11, 12 are controlled into the on state or the off state by a control signal on a master word line MWL. For activating the word line WL, the control circuit 20 generates the low voltage potential VWL on the master word line MWL. As a result, the p-channel transistor 12 is switched into the on state and the n-channel transistor 11 is turned off.
If a voltage generator 40 is driven by a state of the control signal S1 such that the voltage generator 40 generates a high voltage potential VPP on the output side and feeds the high voltage potential VPP onto the driver line WD. Then, the word line WL is connected to the high voltage potential VPP by the transistor 12 controlled into the on state. As a result, the selection transistor AT of the memory cell SZ1 is controlled into the on state, so that the storage capacitor SC is connected to the bit line BL1. Depending on the charge state of the storage capacitor SC, this results in a potential increase or a potential decrease on the bit line BL1, which is amplified by a sense amplifier LV (illustrated in FIG. 2) connected to the bit line.
However, the feeding in of the voltage potential VWL on the master word line MWL simultaneously causes the p-channel transistor 12′ of the second intermediate amplifier to be controlled into the on state. In order that only the memory cell SZ1 is accessed, a voltage generator 40′ connected to the driver line WD′ is driven by the control circuit such that the voltage generator 40′ feeds a ground potential GND onto the driver line. In order to ensure that the selection transistor associated with the memory cell SZ2 is turned off, a further n-channel transistor 13′ is connected in parallel with the n-channel transistor 11′. The further n-channel transistor is additionally controlled into the on state as a result of its control terminal S13′ being driven by the control circuit 20 with a high control voltage potential Vint. A terminal D1 for applying the low voltage potential VWL is thereby conductively connected to the word line WL′. The word line WL′ is thus charged to the low voltage potential VWL, which reliably turns off the selection transistor of the memory cell SZ2.
If neither of the two memory cells SZ1, SZ2 is accessed, then the master word line MWL is driven by the high voltage potential VPP. As a result, the transistors 11 of the first intermediate amplifier and 11′ of the second intermediate amplifier are controlled into the on state, so that the word line WL and the word line WL′ are connected to the low voltage potential VWL. Consequently, the selection transistors of the memory cells SZ1, SZ2 are turned off.
In an area-optimized layout, there is a risk of the two n-channel transistors 11 and 13 not being connected to the word line WL after the fabrication process. A word line having such a defect cannot turn off in controlled fashion the selection transistors that it controls, since a controlled applying the voltage potential VWL onto the word line is not possible. Even though such word lines are identified as defective and repaired, the word lines are still physically situated in the cell array. The word line signal of a repaired word line in the case of which the n-channel transistors of its connected intermediate amplifier are missing may be charged to a high voltage potential via the p-channel transistor, for example, and thus partly activate the selection transistors connected to the defective word line.
In this respect, FIG. 4 shows, for example, a defective word line FWL with its connected intermediate amplifier, in the case of which the two n-channel transistors 11 and 13 are not connected to the word line FWL. The defective word line FWL is replaced by a redundant word line in this case. In order that the selection transistors connected to the defective word line FWL remain permanently turned off, the master word line MWL is driven by the high voltage potential VPP. However, the subthreshold behavior of the p-channel transistor 12 may have the effect that its controllable path is not permanently turned off. The transistor 12 thus behaves like a resistor via which the defective word line FWL is gradually charged to almost the high voltage potential VPP. As a result, for example, the selection transistor AT1 (illustrated in FIG. 4) of the memory cell SZ1 connected to the defective word line FWL attains the on state. The memory cell SZ1 has a leakage current behavior as a result. By the selection transistor AT1 controlled into the on state and behaves like a resistor and by the storage capacitor SC1, the memory cell acts like a low-pass filter connected to the bit line BL.
FIG. 5 shows the potential profile on the bit line BL and the voltage VCFWL established due to the leakage current ICFWL on the storage capacitor SC1 of the memory cell SZ1. When a datum, for example, a high state, is written to the memory cell SZ2, the sense amplifier LV feeds a high voltage potential onto the bit line BL. By the selection transistor AT1 that is partly controlled into the on state, the storage capacitor SC1 of the memory cell SZ1 is slowly charged during the writing time tRAS to the voltage potential VBL of the bit line by a positive leakage current ICFWL. In the precharge phase, during the time tRP, the bit line BL and its complementary bit line/BL are charged to a common precharge potential. During this time, the storage capacitor SC1 is discharged again onto the bit line BL via the selection transistor AT1 controlled into the on state. A negative leakage current ICFWL flows in this case. In the case of short precharge times tRP, the storage capacitor SC1 is not completely discharged. If a high level is subsequently written again to a memory cell connected to the bit line BL, then the storage capacitor SC1 is charged further by the voltage potential fed onto the bit line BL by the sense amplifier LV. In the worst-case scenario, the voltage potential on the storage capacitor SC1 builds up to an ever higher voltage potential.
If a memory cell, for example, the memory cell SZ2, is then accessed in reading fashion, the storage capacitor SC1, as a result of the leakage current ICFWL flowing out of the memory cell SZ1, feeds a charge onto the bit line BL which shifts a small voltage swing, originating from the read-out of the charge state of the storage capacitor of the memory cell SZ2, in an opposite direction. As a consequence, the sense amplifier LV amplifies this signal swing that is directed oppositely to the signal swing of the original storage state of the memory cell SZ2.
On account of component-specific leakage currents, defective word lines that can no longer be connected to the low voltage potential VWL via a transistor of their intermediate amplifier have very different time constants with which the voltages on the defective word line change. Moreover, the defective word lines are influenced by capacitive coupling in the event of access to memory cells in the immediate vicinity. This means that it is often no longer possible to test this fault pattern deterministically within tenable times.
An integrated semiconductor memory with a test circuit used to ascertain whether a word line can no longer be connected to a predetermined voltage potential, for example, a voltage potential for turning off selection transistors, and a method to test whether a word line can no longer be driven by a predetermined voltage potential, for example, a voltage potential for turning off selection transistors, are desirable.